1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit. More particularly, the present invention relates to dynamic random access memories (DRAMs) having a tri-state logic gate circuit using a boosted power supply voltage.
This application is a counterpart of Japanese application Serial Number 259532/1997, filed Sep. 25, 1997, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
FIG. 1 is a schematic diagram showing circuitry according to a conventional DRAM circuit.
The DRAM has circuitry to control the transfer of the stored data from memory cell arrays 100 to sense amplifiers 101, amplifies the transferred result, and outputs the result, by switching each of transfer gates 102 in response to timing signals applied from tri-state logic gate circuits 103.
FIG. 2 is a schematic diagram showing a tri-state logic gate circuit 103 according to a conventional DRAM circuit.
As shown in FIG. 2, the tri-state logic gate circuit 103 is made up of two inverter circuits and a latch circuit. A first inverter circuit includes a P-channel MOS transistor P1 and an N-channel MOS transistor N1. A second inverter circuit includes a P-channel MOS transistor P2 and an N-channel MOS transistor N2. The latch circuit includes P-channel MOS transistors P3 and P4 and N-channel MOS transistors N3 and N4. The tri-state logic gate circuit 103 controls a switching operation between a boosted power supply voltage SBOOST and two other power supply voltages V.sub.cc and V.sub.ss in response to a set signal A. The tri-state logic gate circuit 103 also controls a switching operation between a power supply voltage V.sub.cc and a ground potential V.sub.ss in response to a reset signal A'. Therefore, the tri-state logic gate circuit 103 selectively outputs the boosted power supply voltage SBOOST, the power supply voltage V.sub.cc, and the ground potential V.sub.ss. The boosted power supply voltage SBOOST is a voltage using as a gate signal of the transfer gates 102, and which is generated in an internal integrated circuit based on the power supply voltage V.sub.cc. Further, the boosted power supply voltage SBOOST is V.sub.cc +Vt+.alpha. boosted in order to transfer charges of bit lines to the sense amplifier 101. FIG. 3 is a timing chart showing an operation of a tri-state logic gate circuit according to a conventional DRAM circuit.
The memory cell access operation is as follows.
The reset signal A' maintains an H level. The set signal A maintains an L level. At this time, a P-channel MOS transistor P1 turns off, an N-channel MOS transistor N1 turns on, a P-channel MOS transistor P2 turns on, and an N-channel MOS transistor N2 turns off. As a result, a timing signal TG changes to a level of the boosted power supply voltage SBOOST. Accordingly, the transfer gate 102a turns on, the transfer gate 102b turns off, and bit lines are capable of connecting to the sense amplifier 101. And then, the sense amplifier 101 starts to operate.
The precharge operation is as follows.
The reset signal A' maintains an L level. The set signal A maintains an H level. At this time, a P-channel MOS transistor P1 turns on, an N-channel MOS transistor N1 turns off, a P-channel MOS transistor P2 turns off, and an N-channel MOS transistor N2 turns on. As a result, a level of a timing signal TG becomes a level of the power supply voltage V.sub.cc.
When the memory cell aren't selected, both of the reset signal A' and the set signal A maintain an H level. As a result, a level of a timing signal TG becomes a level of the ground potential V.sub.ss.
Here, back-biases of the P-channel MOS transistors P1 and P2 are the boosted power supply voltage SBOOST, respectively. This reason is that a voltage tolerance of the P-channel MOS transistors P1 and P2 are concerned.